Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
نویسندگان
چکیده
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called “dynamically variable line-size cache (D-VLS cache).” The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a directmapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache∗ . key words: cache, variable line-size, merged DRAM/logic LSIs, high bandwidth
منابع مشابه
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called \dynamically variable line-size cache (D-VLS cache)". The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement...
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